Fix: added contention error image for Chapter 8 (8.3.gif) and updated MDX content. Closes #446 (#448)

Author: naman79820

docs/chapter8/3cverrormessages.mdx

@@ -16,6 +16,6 @@ description: "Cverrormessages page in Chapter8 of CircuitVerse documentation."
 
 2. **Contention Error 1 and 0**: When the circuit is driven by two or more outputs of both HIGH and LOW, the simulator may display this error.
 
-   ![Contention Error 1 and 0](https://i.stack.imgur.com/xW0lC.gif)
+   ![Contention Error 1 and 0](/img/img_chapter8/8.3.gif)
 
 **Resolution:** Logic contention errors indicate a circuit design problem leading to large amounts of power to flow across circuit elements. Revisit your design for some wiring errors or for active multiple output enable lines that are driving a bus or circuit node simultaneously.