diff --git a/docs/chapter3/properties.md b/docs/chapter3/properties.md index cd35999f7..2a9744794 100644 --- a/docs/chapter3/properties.md +++ b/docs/chapter3/properties.md @@ -192,3 +192,31 @@ Table 3.8: Brief description of the different settings available on the **LAYOUT + +## Lite Mode in Simulator + +![drawing](/img/img_chapter3/3.24.png) + +
+ Figure 3.24 +
+ +The Lite Mode is a performance mode that trades visual quality and features for better performance on resource-constrained devices. The Lite mode does the following things: + +1. Reduces Canvas Resolution: Sets DPR to 1 regardless of device (no retina/high-DPI rendering) +2. Slows Down Updates: Makes UI updates 5x less frequent (time *= 5) +3. Disables Minimap: Completely disables minimap rendering and setup +4. Reduces Scaling Complexity: Simplifies canvas scaling calculations + +### Changes due to Lite Mode + +Visual Changes: +1. Lower Resolution: Circuit elements appear less crisp on high-DPI displays +2. No Minimap: The navigation minimap is hidden +3. Slower Responsiveness: UI updates happen less frequently + +When to use Lite mode: +1. Low-end devices with limited graphics performance +2. Battery saving on mobile devices +3. Older computers that struggle with high-resolution rendering +4. Large circuits where performance becomes an issue diff --git a/docs/chapter6/delayvsclock.md b/docs/chapter6/delayvsclock.md index 643cb337b..5abc2cf3b 100644 --- a/docs/chapter6/delayvsclock.md +++ b/docs/chapter6/delayvsclock.md @@ -8,7 +8,7 @@ description: "Delayvsclock page in Chapter6 of CircuitVerse documentation." Before exploring how to visualize a timing diagram for a given circuit, this section explores some key concepts that define the working of the **TIMING DIAGRAM** panel. -## Clock Time (ms): +## Clock Time (ms) The **Clock Time** property attribute in Figure 6.1 refers to the time interval for the half cycle of a circuit. Changing the clock time interval speeds up or slows down the circuit simulation. However, it should be noted that changing the **Delay** attribute for any circuit element doesn't change circuit behavior. This clock frequency is only for demonstration purposes. diff --git a/static/img/img_chapter3/3.24.png b/static/img/img_chapter3/3.24.png new file mode 100644 index 000000000..368075261 Binary files /dev/null and b/static/img/img_chapter3/3.24.png differ