diff --git a/docs/chapter1/1introduction.md b/docs/chapter1/1introduction.md
index 301dafbb..ac974fcc 100644
--- a/docs/chapter1/1introduction.md
+++ b/docs/chapter1/1introduction.md
@@ -1,67 +1,53 @@
---
id: chapter1-introduction
title: "Introduction"
-description: "Introduction page in Chapter1 of CircuitVerse documentation."
-slug : /
+description: "Introduction to CircuitVerse and its features."
+slug: /
---
-# Introduction
-
-
-
-Inspired by Logisim, CircuitVerse is an open-source educational tool for designing and visualizing digital logic circuit simulations in the cloud. Users including educators, students, electronic engineers, and hobbyists can play with digital circuit simulations from their browsers for exploring different “what-if” scenarios. As required, a user can share their creations using unique circuit URLs, or fork different contributions of the CircuitVerse community to yield their curiosity. Figure 1 shares a screenshot of a ripple carry adder simulation built using CircuitVerse.
-
-
-
-
- Figure 1.1: Ripple Carry Adder simulation built using CircuitVerse
-
-
-Developed for educators by educators, the CircuitVerse platform delivers high class learning experience in a scalable way. Educators can manage, track, and achieve their classroom learning goals in a single, powerful solution. They can create and manage different student groups, post different assignments, define submission deadlines and add or export grades (refer Figure 2). Using the CircuitVerse Chrome extension, educators can embed live circuits in their Google Slides and demonstrate concepts without navigating across different tabs. Alternatively, they can also export images or embed iFrames within their webpages.
-
-
-
-
-
- Figure 1.2: Educators can manage, track, and achieve their classroom
- learning goals using CircuitVerse platform
-
-
-
-As the CircuitVerse community grows, educators and students can join the online forums to share ideas, questions, and resources related to teaching and learning digital logic design using CircuitVerse.
-
-
-
-
-
- Figure 1.3: Connect and collaborate on CircuitVerse Forum for sharing ideas,
- questions, and resources related to teaching and learning digital logic
- design
-
-
-
-Watch the below video for a quick demonstration of the CircuitVerse platform.
-
-
-
-
+## What is CircuitVerse?
+
+Inspired by Logisim, **CircuitVerse** is an open-source educational platform for designing and visualizing digital logic circuits directly in the browser. It enables educators, students, electronics engineers, and hobbyists to experiment with digital circuit simulations and explore various "what-if" scenarios.
+
+Users can share their creations using unique circuit URLs or fork projects from the CircuitVerse community to satisfy their curiosity.
+
+
+
+ Figure 1.1: Ripple Carry Adder simulation built using CircuitVerse
+
+
+---
+
+## Classroom Management
+
+Developed for educators by educators, CircuitVerse delivers a **high-quality learning experience** at scale. Educators can:
+
+- Create and manage student groups
+- Assign projects with deadlines
+- Track submissions and export grades
+
+Using the CircuitVerse Chrome extension, instructors can embed live circuits into Google Slides or export simulations as images or iFrames.
+
+
+
+ Figure 1.2: Classroom management features in CircuitVerse
+
+
+---
+
+## Community & Collaboration
+
+As the CircuitVerse community grows, educators and students can connect through online forums to share ideas, ask questions, and collaborate on digital logic design concepts.
+
+
+
+ Figure 1.3: CircuitVerse community forum
+
+
+---
+
+## Video Overview
+
+Watch the video below for a quick demonstration of the CircuitVerse platform:
+
+
\ No newline at end of file
diff --git a/docs/chapter1/1introduction.mdx b/docs/chapter1/1introduction.mdx
new file mode 100644
index 00000000..8579c7db
--- /dev/null
+++ b/docs/chapter1/1introduction.mdx
@@ -0,0 +1,57 @@
+---
+id: chapter1-introduction
+title: "Introduction"
+description: "Introduction to CircuitVerse and its features."
+slug: /
+---
+
+## What is CircuitVerse?
+
+Inspired by Logisim, **CircuitVerse** is an open-source educational platform for designing and visualizing digital logic circuits directly in the browser. It enables educators, students, electronics engineers, and hobbyists to experiment with digital circuit simulations and explore various "what-if" scenarios.
+
+Users can share their creations using unique circuit URLs or fork projects from the CircuitVerse community to satisfy their curiosity.
+
+
+
+*Figure 1.1: Ripple Carry Adder simulation built using CircuitVerse*
+
+
+
+## Classroom Management
+
+Developed for educators by educators, CircuitVerse delivers a **high-quality learning experience** at scale. Educators can:
+
+- Create and manage student groups
+- Assign projects with deadlines
+- Track submissions and export grades
+
+Using the CircuitVerse Chrome extension, instructors can embed live circuits into Google Slides or export simulations as images or iFrames.
+
+
+
+*Figure 1.2: Classroom management features in CircuitVerse*
+
+
+
+## Community & Collaboration
+
+As the CircuitVerse community grows, educators and students can connect through online forums to share ideas, ask questions, and collaborate on digital logic design concepts.
+
+
+
+*Figure 1.3: CircuitVerse community forum*
+
+
+
+## Video Overview
+
+Watch the video below for a quick demonstration of the CircuitVerse platform:
+
+
diff --git a/docs/chapter4/5decodersandplexers.md b/docs/chapter4/5decodersandplexers.md
new file mode 100644
index 00000000..c716dee4
--- /dev/null
+++ b/docs/chapter4/5decodersandplexers.md
@@ -0,0 +1,700 @@
+---
+id: chapter4-muxandplex
+title: "Muxandplex"
+description: "Muxandplex page in Chapter4 of CircuitVerse documentation."
+---
+
+# Decoders & Plexers
+
+CircuitVerse features the following circuit elements in this category:
+
+1. [Multiplexer](#multiplexer)
+2. [Demultiplexer](#demultiplexer)
+3. [BitSelector](#bitselector)
+4. [Most Significant Bit (MSB) Detector](#most-significant-bit-msb-detector)
+5. [Least Significant Bit (LSB) Detector](#least-significant-bit-lsb-detector)
+6. [Priority Encoder](#priority-encoder)
+7. [Decoder](#decoder)
+8. [Parity Generator & Parity Detector](#parity-generator--parity-detector)
+
+## Multiplexer
+
+A **Multiplexer** selectively passes only one of the inputs provided to it using a control signal. The number of inputs is always a power of 2. If there are N control bits, then there can be a maximum of 2^N inputs.
+
+> Properties that can be customized in the **PROPERTIES** panel include: **BitWidth, Control Signal Size**
+
+Consider a 2 to 1 multiplexer that takes two single-bit inputs (T1 and T2), a single-bit control signal (S) and has an output (Out). Using Table 4.1, you can verify the behavior of a 2 to 1 multiplexer.
+
+Table 4.1: Truth table of a 2 to 1 multiplexer
+
+
+
+
S
+
Out
+
+
+
0
+
T1
+
+
+
1
+
T2
+
+
+
+
+
+Using Table 4.2, you can verify the behavior of the **Multiplexer** circuit element in the live circuit of a 4 to 1 multiplexer embedded below:
+
+Table 4.2: Truth table of a 4 to 1 multiplexer
+
+
+
+
S1
+
S0
+
Out
+
+
+
0
+
0
+
T1
+
+
+
0
+
1
+
T2
+
+
+
1
+
0
+
T3
+
+
+
1
+
1
+
T4
+
+
+
+
+
+## Demultiplexer
+
+A **Demultiplexer** takes an input and passes it to only one of outputs using a control signal. The number of outputs is always a power of 2. If there are N control bits, we can choose to pass the output to any one of the 2^N output lines.
+
+> Properties that can be customized in the **PROPERTIES** panel include: **BitWidth, Control Signal Size**
+
+In the live circuit embedded below, a 1 to 2 demultiplexer takes in a single-bit input (T), a single-bit control signal (S) and two single-bit outputs (O1 and O2). Table 4.3 displays the truth table of a 1 to 2 demultiplexer.
+
+Table 4.3: Truth table of a 1 to 2 demultiplexer
+
+
+
+
S
+
O1
+
O2
+
+
+
0
+
T
+
0
+
+
+
1
+
0
+
T
+
+
+
+
+
+In another example of a live circuit embedded below, a 1 to 4 demultiplexer takes in a three-bit input and a two-bit control signal. Table 4.4 displays the truth table of a 1 to 4 demultiplexer.
+
+Table 4.4: Truth table of a 1 to 4 demultiplexer
+
+
+
+
S1
+
S0
+
O1
+
O2
+
O3
+
O4
+
+
+
0
+
0
+
T
+
0
+
0
+
0
+
+
+
0
+
1
+
0
+
T
+
0
+
0
+
+
+
1
+
0
+
0
+
0
+
T
+
0
+
+
+
1
+
1
+
0
+
0
+
0
+
T
+
+
+
+
+
+## BitSelector
+
+As its name suggests, the **BitSelector** circuit element takes a single or multi-bit input and outputs the bit that must be isolated using a single or multi-bit select line. The select line value indicates the specific bit that must be isolated within its body in decimal form.
+
+> Properties that can be customized in the **PROPERTIES** panel include: **BitWidth, Selector Bit Width**
+
+In the live circuit embedded below, a **BitSelector** with a four-bit input is used. Each of its bits can be addressed separately as T3, T2, T1, T0 (from most significant to least significant). It also includes a two-bit select line (S1 and S0) and a single-bit output (Out). Table 4.5 displays the truth table of a four-bit BitSelector.
+
+Table 4.5: Truth table of a four-bit bit selector
+
+
+
+
S1
+
S0
+
Out
+
+
+
0
+
0
+
T0
+
+
+
0
+
1
+
T1
+
+
+
1
+
0
+
T2
+
+
+
1
+
1
+
T3
+
+
+
+
+
+## Most Significant Bit (MSB) Detector
+
+The **Most Significant Bit (MSB)** detector circuit element outputs the position of the most significant (leftmost) `1` in the input.
+
+An enable output is also provided to indicate whether the MSB detector is active.
+The bit position of the MSB is displayed in decimal form within the body of the MSB detector.
+
+If all input bits are `0`, the enable output indicates inactivity.
+
+You can verify the behavior of the **Most Significant Bit (MSB)** detector circuit element with a four-bit input in the live circuit embedded below:
+
+
+
+## Least Significant Bit (LSB) Detector
+
+The **Least Significant Bit (LSB)** detector circuit element outputs the position of the least significant (rightmost) `1` in the input.
+
+An enable output is also provided to indicate whether the LSB detector is active.
+The bit position of the LSB is displayed in decimal form within the body of the LSB detector.
+
+If all input bits are `0`, the enable output indicates inactivity.
+
+You can verify the behavior of the **Least Significant Bit (LSB)** detector circuit element with a four-bit input in the live circuit embedded below:
+
+
+
+## Priority Encoder
+
+The **Priority Encoder** circuit element works similarly to the **MSB and LSB** detectors. There is a specific output based on the bit position of the MSB, irrespective of the lesser significant bits. An enable input is also provided to activate/deactivate the priority encoder. If there are N outputs, there will be 2^N inputs.
+
+In the live circuit embedded below, a **Priority Encoder** with four single-bit inputs (T3, T2, T1, and T0 from most to least-significant bit) and two single-bit outputs (O2 and O1 from most to least-significant bit). Table 4.6 displays the truth table of the four-input priority encoder.
+
+> Properties that can be customized in the **PROPERTIES** panel include: **BitWidth**
+
+Table 4.6: Truth table of a four-input priority encoder
+
+
+
+
T3
+
T2
+
T1
+
T0
+
O2
+
O1
+
+
+
0
+
0
+
0
+
1
+
0
+
0
+
+
+
0
+
0
+
1
+
X
+
0
+
1
+
+
+
0
+
1
+
X
+
X
+
1
+
0
+
+
+
1
+
X
+
X
+
X
+
1
+
1
+
+
+
+
+
+## Decoder
+
+The **Decoder** circuit element includes N input bits and has 2ⁿ output lines, where only one output is HIGH for each unique input combination.
+
+In the live circuit embedded below, a **Decoder** with a single two-bit input (T1 and T0 from most to least-significant bit) and four single-bit output lines (O4, O3, O2, and O1 from most to least-significant bit). For the input values set in T1 and T0, the corresponding output line (O4, O3, O2, and O1) is HIGH. Table 4.7 displays the truth table for a two-bit decoder.
+
+> Properties that can be customized in the **PROPERTIES** panel include: **BitWidth**
+
+Table 4.7: Truth table of a two-bit decoder
+
+
+
+
T1
+
T0
+
O4
+
O3
+
O2
+
O1
+
+
+
0
+
0
+
0
+
0
+
0
+
1
+
+
+
0
+
1
+
0
+
0
+
1
+
0
+
+
+
1
+
0
+
0
+
1
+
0
+
0
+
+
+
1
+
1
+
1
+
0
+
0
+
0
+
+
+
+
+
+## Parity Generator & Parity Detector
+
+The **Parity Generator** and **Parity Detector** combinational circuit elements are used together for error-tolerant data transmission. The **Parity Generator** circuit element is used by the sender, and the **Parity Detector** circuit element is used by the receiver.
+
+### Parity Generator
+
+The **Parity Generator** circuit element generates a parity bit which is later used by parity detectors to detect errors in data transmission. The parity bit is added to the original message that must be sent.
+
+If the input message of an even parity generator has an even number of `1`s, the parity bit will be 0. On the other hand, if there are an odd number of `1`s, the parity bit generated will be 1. Table 4.8 displays the truth table for an even three-bit input parity generator.
+
+Table 4.8: Truth table for an even three-bit parity generator
+
+
+
+
A
+
B
+
C
+
PARITY BIT (P)
+
+
+
0
+
0
+
0
+
0
+
+
+
0
+
0
+
1
+
1
+
+
+
0
+
1
+
0
+
1
+
+
+
0
+
1
+
1
+
0
+
+
+
1
+
0
+
0
+
1
+
+
+
1
+
0
+
1
+
0
+
+
+
1
+
1
+
0
+
0
+
+
+
1
+
1
+
1
+
1
+
+
+
+If the input message of an odd parity generator has an even number of `1`s, the parity bit will be 1. Alternatively, if there are an odd number of `1`s, the parity bit generated will be 0. The parity bit generated is then added to the message to be sent. Table 4.9 displays the truth table for an odd three-bit input parity generator.
+
+Table 4.9: Truth table for an odd three-bit parity generator
+
+
+
+
A
+
B
+
C
+
PARITY BIT (P)
+
+
+
0
+
0
+
0
+
1
+
+
+
0
+
0
+
1
+
0
+
+
+
0
+
1
+
0
+
0
+
+
+
0
+
1
+
1
+
1
+
+
+
1
+
0
+
0
+
0
+
+
+
1
+
0
+
1
+
1
+
+
+
1
+
1
+
0
+
1
+
+
+
1
+
1
+
1
+
0
+
+
+
+### Parity Detector
+
+The **Parity Detector** circuit element receives the message and checks it for errors. If an error is detected, the parity error check bit gives `1` as output and `0` when no error is detected. Table 4.10 and Table 4.11 display the truth tables for an even and odd three-bit input parity detector, respectively.
+
+
+
+
A
+
B
+
C
+
P
+
PARITY ERROR CHECK
+
+
+
0
0
0
1
1
+
+
+
0
0
1
0
1
+
+
+
0
0
1
1
0
+
+
+
0
1
0
0
1
+
+
+
0
1
0
1
0
+
+
+
0
1
1
0
0
+
+
+
0
1
1
1
1
+
+
+
1
0
0
0
1
+
+
+
1
0
0
1
0
+
+
+
1
0
1
0
0
+
+
+
1
0
1
1
1
+
+
+
1
1
0
0
0
+
+
+
1
1
0
1
1
+
+
+
1
1
1
0
1
+
+
+
1
1
1
1
0
+
+
+
+
+
+
+
A
+
B
+
C
+
P
+
PARITY ERROR CHECK
+
+
+
0
0
0
0
1
+
+
+
0
0
0
1
0
+
+
+
0
0
1
0
0
+
+
+
0
0
1
1
1
+
+
+
0
1
0
0
0
+
+
+
0
1
0
1
1
+
+
+
0
1
1
0
1
+
+
+
0
1
1
1
0
+
+
+
1
0
0
0
0
+
+
+
1
0
0
1
1
+
+
+
1
0
1
0
1
+
+
+
1
0
1
1
0
+
+
+
1
1
0
0
1
+
+
+
1
1
0
1
0
+
+
+
1
1
1
0
0
+
+
+
1
1
1
1
1
+
+
+
+Although the parity detector can detect most errors, some of its limitations include:
+
+- Error is detected only if there are an odd number of error bits.
+- Error in parity bit might lead to error detection despite correct transmission.
+- Parity detector will not be able to detect errors where both parity and data bits have such an error that matches the parity bit.
+
+You can verify the same in the live circuit embedded below:
+
+
\ No newline at end of file
diff --git a/docs/chapter4/5muxandplex.md b/docs/chapter4/5muxandplex.md
index 0f93ef44..c716dee4 100644
--- a/docs/chapter4/5muxandplex.md
+++ b/docs/chapter4/5muxandplex.md
@@ -254,7 +254,12 @@ Table 4.5: Truth table of a four-bit bit selector
## Most Significant Bit (MSB) Detector
-The **Most Significant Bit (MSB)** detector circuit element outputs the bit position of the most significant bit of the input. In other words, it outputs the bit position of the rightmost bit. An enable output is also provided to show if the MSB detector is active. The bit position of the MSB is also shown in decimal form within the body of the MSB detector.
+The **Most Significant Bit (MSB)** detector circuit element outputs the position of the most significant (leftmost) `1` in the input.
+
+An enable output is also provided to indicate whether the MSB detector is active.
+The bit position of the MSB is displayed in decimal form within the body of the MSB detector.
+
+If all input bits are `0`, the enable output indicates inactivity.
You can verify the behavior of the **Most Significant Bit (MSB)** detector circuit element with a four-bit input in the live circuit embedded below:
@@ -273,7 +278,12 @@ You can verify the behavior of the **Most Significant Bit (MSB)** detector circu
## Least Significant Bit (LSB) Detector
-The **Least Significant Bit (LSB)** detector circuit element outputs the bit position of the least significant bit of the input. In other words, it outputs the bit position of the leftmost bit. An enable output is also provided to show if the LSB detector is active. The bit position of the LSB is also shown in decimal form within the body of the LSB detector.
+The **Least Significant Bit (LSB)** detector circuit element outputs the position of the least significant (rightmost) `1` in the input.
+
+An enable output is also provided to indicate whether the LSB detector is active.
+The bit position of the LSB is displayed in decimal form within the body of the LSB detector.
+
+If all input bits are `0`, the enable output indicates inactivity.
You can verify the behavior of the **Least Significant Bit (LSB)** detector circuit element with a four-bit input in the live circuit embedded below:
@@ -358,7 +368,7 @@ Table 4.6: Truth table of a four-input priority encoder
## Decoder
-The **Decoder** circuit element includes N input bits and has 2^N output lines.
+The **Decoder** circuit element includes N input bits and has 2ⁿ output lines, where only one output is HIGH for each unique input combination.
In the live circuit embedded below, a **Decoder** with a single two-bit input (T1 and T0 from most to least-significant bit) and four single-bit output lines (O4, O3, O2, and O1 from most to least-significant bit). For the input values set in T1 and T0, the corresponding output line (O4, O3, O2, and O1) is HIGH. Table 4.7 displays the truth table for a two-bit decoder.
diff --git a/src/css/custom.css b/src/css/custom.css
index f290fe31..6d003233 100644
--- a/src/css/custom.css
+++ b/src/css/custom.css
@@ -5,4 +5,24 @@
height: auto;
aspect-ratio: 4 / 3;
}
+}
+
+/* === Figure and Caption Styling === */
+figure {
+ margin: 1.5rem 0;
+ text-align: center;
+}
+
+figure img {
+ max-width: 100%;
+ height: auto;
+ border-radius: 8px;
+ box-shadow: 0 2px 8px rgba(0, 0, 0, 0.1);
+}
+
+figcaption {
+ margin-top: 0.5rem;
+ font-size: 0.9rem;
+ color: var(--ifm-color-emphasis-600);
+ font-style: italic;
}
\ No newline at end of file
+ 
+ 
+