diff --git a/docs/chapter4/8misc.md b/docs/chapter4/8misc.md index d8bc7cfa6..424008d19 100644 --- a/docs/chapter4/8misc.md +++ b/docs/chapter4/8misc.md @@ -17,6 +17,7 @@ description: "Misc page in Chapter4 of CircuitVerse documentation." 9. [Unequal Split](#unequal-split) 10. [Flag](#flag) 11. [Two's Complement](#twos-complement) +12. [Force Gate](#force-gate) ## ALU @@ -571,3 +572,73 @@ You can verify the behavior of the **Two’s Complement** circuit element in the mozAllowFullScreen allowFullScreen > + +## Force Gate + +The **Force Gate** is a logical circuit element used to override and control binary values in a connected circuit. It allows users to force specific logic values during simulation, enabling effective testing, debugging, and custom behavior analysis. + +Unlike standard logic gates, the Force Gate does not compute outputs based on logical operations. Instead, it directly applies a user-defined value to the connected input. + +>Properties that can be customized in the **PROPERTIES** panel include: **Direction, BitWidth, Delay, Label** + +![drawing](/img/img_chapter4/4.25.png) + +
Figure 4.25: Relevant attributes for the Force Gate element
+ +Table 4.26: Truth table for a Force Gate + + + + + + + + + + + + + + + + + + + + + + + + + + +
Enable + Input + Output +
0 + 0 + 0 +
0 + 1 + 0 +
1 + 0 + 1 +
1 + 1 + 1 +
+ +>- When Enable is HIGH, the output is forced HIGH regardless of the input value. +>- When Enable is LOW, the output is forced LOW regardless of the input value. + + diff --git a/static/img/img_chapter4/4.25.png b/static/img/img_chapter4/4.25.png new file mode 100644 index 000000000..34020ee8d Binary files /dev/null and b/static/img/img_chapter4/4.25.png differ