Skip to content

Commit 23207ac

Browse files
Support Ryzen 9000 Series (#1469)
* Support Ryzen 9000 Series LibreHardwareMonitor/LibreHardwareMonitor#1467 LibreHardwareMonitor/LibreHardwareMonitor#1418 * Update Amd17Cpu.cs * Update Amd17Cpu.cs --------- Co-authored-by: PhyxionNL <7643972+PhyxionNL@users.noreply.github.com>
1 parent ab2ce7a commit 23207ac

3 files changed

Lines changed: 17 additions & 4 deletions

File tree

LibreHardwareMonitorLib/Hardware/Cpu/Amd17Cpu.cs

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -197,7 +197,8 @@ public void UpdateSensors()
197197
supportsPerCcdTemperatures = true;
198198
break;
199199

200-
case 0x61:
200+
case 0x61: //Zen 4
201+
case 0x44: //Zen 5
201202
sviPlane0Offset = F17H_M01H_SVI + 0x10;
202203
sviPlane1Offset = F17H_M01H_SVI + 0xC;
203204
supportsPerCcdTemperatures = true;
@@ -289,7 +290,7 @@ public void UpdateSensors()
289290
{
290291
for (uint i = 0; i < _ccdTemperatures.Length; i++)
291292
{
292-
if (cpuId.Model == 0x61)
293+
if (cpuId.Model is 0x61 or 0x44) // Raphael or GraniteRidge
293294
Ring0.WritePciConfig(0x00, FAMILY_17H_PCI_CONTROL_REGISTER, F17H_M61H_CCD1_TEMP + (i * 0x4));
294295
else
295296
Ring0.WritePciConfig(0x00, FAMILY_17H_PCI_CONTROL_REGISTER, F17H_M70H_CCD1_TEMP + (i * 0x4));
@@ -348,7 +349,7 @@ public void UpdateSensors()
348349
double vcc;
349350
uint svi0PlaneXVddCor;
350351

351-
if (cpuId.Model is 0x61) // Readout not working for Ryzen 7000.
352+
if (cpuId.Model is 0x61 or 0x44) // Readout not working for Ryzen 7000/9000.
352353
smuSvi0Tfn |= 0x01 | 0x02;
353354

354355
// Core (0x01).

LibreHardwareMonitorLib/Hardware/Cpu/CpuGroup.cs

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -51,6 +51,7 @@ public CpuGroup(ISettings settings)
5151
break;
5252
case 0x17:
5353
case 0x19:
54+
case 0x1A:
5455
_hardware.Add(new Amd17Cpu(index, coreThreads, settings));
5556
break;
5657
default:

LibreHardwareMonitorLib/Hardware/RyzenSMU.cs

Lines changed: 12 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -191,6 +191,11 @@ private static CpuCodeName GetCpuCodeName(uint family, uint model, uint packageT
191191
0x61 => CpuCodeName.Raphael,
192192
_ => CpuCodeName.Undefined
193193
},
194+
0x1A => model switch
195+
{
196+
0x44 => CpuCodeName.GraniteRidge,
197+
_ => CpuCodeName.Undefined
198+
},
194199
_ => CpuCodeName.Undefined
195200
};
196201
}
@@ -232,6 +237,7 @@ private bool SetAddresses(CpuCodeName codeName)
232237
case CpuCodeName.Matisse:
233238
case CpuCodeName.Vermeer:
234239
case CpuCodeName.Raphael:
240+
case CpuCodeName.GraniteRidge:
235241
_cmdAddr = 0x3B10524;
236242
_rspAddr = 0x3B10570;
237243
_argsAddr = 0x3B10A40;
@@ -424,6 +430,7 @@ private void SetupPmTableSize()
424430
break;
425431

426432
case CpuCodeName.Raphael:
433+
case CpuCodeName.GraniteRidge:
427434
switch (_pmTableVersion)
428435
{
429436
case 0x00540004:
@@ -464,6 +471,7 @@ private bool GetPmTableVersion(ref uint version)
464471
fn = 0x06;
465472
break;
466473
case CpuCodeName.Raphael:
474+
case CpuCodeName.GraniteRidge:
467475
fn = 0x05;
468476
break;
469477
default:
@@ -553,6 +561,7 @@ private void SetupDramBaseAddr()
553561
switch (_cpuCodeName)
554562
{
555563
case CpuCodeName.Raphael:
564+
case CpuCodeName.GraniteRidge:
556565
fn[0] = 0x04;
557566
SetupAddrClass1(fn);
558567
return;
@@ -594,6 +603,7 @@ public bool TransferTableToDram()
594603
switch (_cpuCodeName)
595604
{
596605
case CpuCodeName.Raphael:
606+
case CpuCodeName.GraniteRidge:
597607
fn = 0x03;
598608
break;
599609
case CpuCodeName.Matisse:
@@ -759,6 +769,7 @@ private enum CpuCodeName
759769
Cezanne,
760770
Milan,
761771
Dali,
762-
Raphael
772+
Raphael,
773+
GraniteRidge
763774
}
764775
}

0 commit comments

Comments
 (0)