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1 parent 6fef482 commit 1180e81Copy full SHA for 1180e81
port/wch/ch32v/src/cpus/main.zig
@@ -254,7 +254,15 @@ pub const startup_logic = struct {
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}
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// Enable interrupts.
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- csr.mtvec.write(.{ .mode0 = 1, .mode1 = 1, .base = 0 });
+ // Set mtvec.base to (vector_table_address - 4) >> 2 so that interrupt N
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+ // jumps to the correct handler regardless of any padding between _reset_vector
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+ // and vector_table.
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+ const vtable_addr = @intFromPtr(&vector_table);
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+ csr.mtvec.write(.{
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+ .mode0 = 1, // Interrupt entry for each interrupt
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+ .mode1 = 1, // Use absolute addresses
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+ .base = @intCast((vtable_addr - 4) >> 2),
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+ });
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csr.mstatus.write(.{
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.mie = 1,
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.mpie = 1,
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