@@ -739,14 +739,10 @@ static int rtmdio_839x_setup_ctrl(struct rtmdio_ctrl *ctrl)
739739
740740static int rtmdio_930x_setup_ctrl (struct rtmdio_ctrl * ctrl )
741741{
742- unsigned int mask , val ;
743-
744742 /* Define C22/C45 bus feature set */
745- for (int smi_bus = 0 ; smi_bus < RTMDIO_MAX_SMI_BUSSES ; smi_bus ++ ) {
746- mask = BIT (16 + smi_bus );
747- val = ctrl -> bus [smi_bus ].is_c45 ? mask : 0 ;
748- regmap_update_bits (ctrl -> map , RTMDIO_930X_SMI_GLB_CTRL , mask , val );
749- }
743+ for (int smi_bus = 0 ; smi_bus < RTMDIO_MAX_SMI_BUSSES ; smi_bus ++ )
744+ regmap_assign_bits (ctrl -> map , RTMDIO_930X_SMI_GLB_CTRL ,
745+ BIT (16 + smi_bus ), ctrl -> bus [smi_bus ].is_c45 );
750746
751747 return 0 ;
752748}
@@ -770,14 +766,12 @@ static void rtmdio_930x_setup_polling(struct rtmdio_ctrl *ctrl)
770766 regmap_update_bits (ctrl -> map , RTMDIO_930X_SMI_MAC_TYPE_CTRL , mask , val );
771767
772768 /* polling via standard or resolution register */
773- mask = BIT (20 + ctrl -> port [pn ].smi_bus );
774- val = phyinfo .has_res_reg ? mask : 0 ;
775- regmap_update_bits (ctrl -> map , RTMDIO_930X_SMI_GLB_CTRL , mask , val );
769+ regmap_assign_bits (ctrl -> map , RTMDIO_930X_SMI_GLB_CTRL ,
770+ BIT (20 + ctrl -> port [pn ].smi_bus ), phyinfo .has_res_reg );
776771
777772 /* proprietary Realtek 1G/2.5 lite polling */
778- mask = BIT (pn );
779- val = phyinfo .has_giga_lite ? mask : 0 ;
780- regmap_update_bits (ctrl -> map , RTMDIO_930X_SMI_PRVTE_POLLING_CTRL , mask , val );
773+ regmap_assign_bits (ctrl -> map , RTMDIO_930X_SMI_PRVTE_POLLING_CTRL ,
774+ BIT (pn ), phyinfo .has_giga_lite );
781775
782776 /* special duplex/advertisement polling registers */
783777 if (phyinfo .poll_duplex || phyinfo .poll_adv_1000 || phyinfo .poll_lpa_1000 ) {
@@ -830,24 +824,17 @@ static void rtmdio_931x_setup_polling(struct rtmdio_ctrl *ctrl)
830824 val = RTMDIO_931X_SMI_PHY_ABLTY_MDIO << (ffs (mask ) - 1 );
831825 regmap_update_bits (ctrl -> map , RTMDIO_931X_SMI_PHY_ABLTY_GET_SEL + (pn / 16 ) * 4 ,
832826 mask , val );
833- mask = val = 0 ;
834827
835828 /* PRVTE0 polling */
836- mask |= BIT (20 + smi_bus );
837- if (phyinfo .has_res_reg )
838- val |= BIT (20 + smi_bus );
839-
829+ regmap_assign_bits (ctrl -> map , RTMDIO_931X_SMI_GLB_CTRL0 ,
830+ BIT (20 + smi_bus ), phyinfo .has_res_reg );
840831 /* PRVTE1 polling */
841- mask |= BIT (24 + smi_bus );
842- if (phyinfo .force_res )
843- val |= BIT (24 + smi_bus );
844-
845- regmap_update_bits (ctrl -> map , RTMDIO_931X_SMI_GLB_CTRL0 , mask , val );
832+ regmap_assign_bits (ctrl -> map , RTMDIO_931X_SMI_GLB_CTRL0 ,
833+ BIT (24 + smi_bus ), phyinfo .force_res );
846834
847835 /* polling std. or proprietary format (bit 0 of SMI_SETX_FMT_SEL) */
848- mask = BIT (smi_bus * 2 );
849- val = phyinfo .force_res ? mask : 0 ;
850- regmap_update_bits (ctrl -> map , RTMDIO_931X_SMI_GLB_CTRL1 , mask , val );
836+ regmap_assign_bits (ctrl -> map , RTMDIO_931X_SMI_GLB_CTRL1 ,
837+ BIT (smi_bus * 2 ), phyinfo .force_res );
851838
852839 /* special polling registers */
853840 if (phyinfo .poll_duplex || phyinfo .poll_adv_1000 || phyinfo .poll_lpa_1000 ) {
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