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generic: 6.18: import updated standalone PCS handling
Import pending series introducing support for standalone PCS drivers. This has previously already been used by the airoha target, and is also the base for the closer-to-upstream patches for MediaTek MT7988 10G SerDes support. In order to not having to diverge from upstream also backport series for standardized handling for PHY and PCS SerDes pair polarity. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
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Lines changed: 4124 additions & 835 deletions

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‎target/linux/ath79/patches-6.18/700-phy-add-ath79-usb-phys.patch‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,7 @@ Signed-off-by: John Crispin <john@phrozen.org>
1515

1616
--- a/drivers/phy/Kconfig
1717
+++ b/drivers/phy/Kconfig
18-
@@ -25,6 +25,22 @@ config GENERIC_PHY_MIPI_DPHY
18+
@@ -47,6 +47,22 @@ config GENERIC_PHY_MIPI_DPHY
1919
Provides a number of helpers a core functions for MIPI D-PHY
2020
drivers to us.
2121

@@ -40,9 +40,9 @@ Signed-off-by: John Crispin <john@phrozen.org>
4040
depends on OF && (ARCH_LPC18XX || COMPILE_TEST)
4141
--- a/drivers/phy/Makefile
4242
+++ b/drivers/phy/Makefile
43-
@@ -4,6 +4,8 @@
44-
#
45-
43+
@@ -6,6 +6,8 @@
44+
obj-$(CONFIG_PHY_COMMON_PROPS) += phy-common-props.o
45+
obj-$(CONFIG_PHY_COMMON_PROPS_TEST) += phy-common-props-test.o
4646
obj-$(CONFIG_GENERIC_PHY) += phy-core.o
4747
+obj-$(CONFIG_PHY_AR7100_USB) += phy-ar7100-usb.o
4848
+obj-$(CONFIG_PHY_AR7200_USB) += phy-ar7200-usb.o

‎target/linux/generic/backport-6.18/702-v7.0-net-phylink-fix-NULL-pointer-deref-in-phylink_major_.patch‎

Lines changed: 79 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,79 @@
1+
From 0e4d7df2f3b2e59c1bccc09ea099b7a6c2dda886 Mon Sep 17 00:00:00 2001
2+
From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
3+
Date: Wed, 28 Jan 2026 10:51:56 +0000
4+
Subject: [PATCH] net: phylink: fix NULL pointer deref in
5+
phylink_major_config()
6+
7+
When a MAC driver returns a PCS for an interface mode, and then we
8+
attempt to switch to a different mode that doesn't require a PCS,
9+
this causes phylink to oops:
10+
11+
Unable to handle kernel NULL pointer dereference at virtual address 0000000000000010
12+
Mem abort info:
13+
ESR = 0x0000000096000044
14+
EC = 0x25: DABT (current EL), IL = 32 bits
15+
SET = 0, FnV = 0
16+
EA = 0, S1PTW = 0
17+
FSC = 0x04: level 0 translation fault
18+
Data abort info:
19+
ISV = 0, ISS = 0x00000044, ISS2 = 0x00000000
20+
CM = 0, WnR = 1, TnD = 0, TagAccess = 0
21+
GCS = 0, Overlay = 0, DirtyBit = 0, Xs = 0
22+
user pgtable: 4k pages, 48-bit VAs, pgdp=0000000137f96000
23+
[0000000000000010] pgd=0000000000000000, p4d=0000000000000000
24+
Internal error: Oops: 0000000096000044 [#1] SMP
25+
Modules linked in: --
26+
CPU: 1 UID: 0 PID: 55 Comm: kworker/u33:0 Not tainted 6.19.0-rc5-00581-g73cb8467a63e #1 PREEMPT
27+
Hardware name: Qualcomm Technologies, Inc. Lemans Ride Rev3 (DT)
28+
Workqueue: events_power_efficient phylink_resolve
29+
pstate: 60400005 (nZCv daif +PAN -UAO -TCO -DIT -SSBS +BTYPE=--)
30+
pc : phylink_major_config+0x408/0x948
31+
lr : phylink_major_config+0x3fc/0x948
32+
sp : ffff800080353c60
33+
x29: ffff800080353cb0 x28: ffffb305068a8a00 x27: ffffb305068a8000
34+
x26: ffff000080092100 x25: 0000000000000000 x24: 0000000000000000
35+
x23: 0000000000000001 x22: 0000000000000000 x21: ffffb3050555b3d0
36+
x20: ffff800080353d10 x19: ffff0000b6059400 x18: 00000000ffffffff
37+
x17: 74756f2f79687020 x16: ffffb305045e4f18 x15: 6769666e6f632072
38+
x14: 6f6a616d203a3168 x13: 782d657361623030 x12: ffffb305068c6a98
39+
x11: 0000000000000583 x10: 0000000000000018 x9 : ffffb305068c6a98
40+
x8 : 0000000100006583 x7 : 0000000000000000 x6 : ffff00008083cc40
41+
x5 : ffff00008083cc40 x4 : 0000000000000001 x3 : 0000000000000001
42+
x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff0000b269e5a8
43+
Call trace:
44+
phylink_major_config+0x408/0x948 (P)
45+
phylink_resolve+0x294/0x6e4
46+
process_one_work+0x148/0x28c
47+
worker_thread+0x2d8/0x3d8
48+
kthread+0x134/0x208
49+
ret_from_fork+0x10/0x20
50+
Code: d63f0020 f9400e60 b4000040 f900081f (f9000ad3)
51+
---[ end trace 0000000000000000 ]---
52+
53+
This is caused by "pcs" being NULL when we attempt to execute:
54+
55+
pcs->phylink = pl;
56+
57+
Make this conditional on pcs being non-null.
58+
59+
Fixes: 486dc391ef43 ("net: phylink: allow mac_select_pcs() to remove a PCS")
60+
Reported-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
61+
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
62+
Link: https://patch.msgid.link/E1vl39Q-00000006utm-229h@rmk-PC.armlinux.org.uk
63+
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
64+
---
65+
drivers/net/phy/phylink.c | 3 ++-
66+
1 file changed, 2 insertions(+), 1 deletion(-)
67+
68+
--- a/drivers/net/phy/phylink.c
69+
+++ b/drivers/net/phy/phylink.c
70+
@@ -1287,7 +1287,8 @@ static void phylink_major_config(struct
71+
if (pl->pcs)
72+
pl->pcs->phylink = NULL;
73+
74+
- pcs->phylink = pl;
75+
+ if (pcs)
76+
+ pcs->phylink = pl;
77+
78+
pl->pcs = pcs;
79+
}

‎target/linux/generic/backport-6.18/703-v7.0-net-phylink-simplify-phylink_resolve-phylink_major_c.patch‎

Lines changed: 61 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,61 @@
1+
From 7bf588dc62a05c1866efe098e1b188fd879aa2cf Mon Sep 17 00:00:00 2001
2+
From: Vladimir Oltean <vladimir.oltean@nxp.com>
3+
Date: Mon, 19 Jan 2026 14:19:51 +0200
4+
Subject: [PATCH] net: phylink: simplify phylink_resolve() ->
5+
phylink_major_config() path
6+
7+
This is a trivial change with no functional effect which replaces the
8+
pattern:
9+
10+
if (a) {
11+
if (b) {
12+
do_stuff();
13+
}
14+
}
15+
16+
with:
17+
18+
if (a && b) {
19+
do_stuff();
20+
};
21+
22+
The purpose is to reduce the delta of a subsequent functional change.
23+
24+
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
25+
Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
26+
Link: https://patch.msgid.link/20260119121954.1624535-2-vladimir.oltean@nxp.com
27+
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
28+
---
29+
drivers/net/phy/phylink.c | 20 +++++++++-----------
30+
1 file changed, 9 insertions(+), 11 deletions(-)
31+
32+
--- a/drivers/net/phy/phylink.c
33+
+++ b/drivers/net/phy/phylink.c
34+
@@ -1681,18 +1681,16 @@ static void phylink_resolve(struct work_
35+
if (pl->act_link_an_mode != MLO_AN_FIXED)
36+
phylink_apply_manual_flow(pl, &link_state);
37+
38+
- if (mac_config) {
39+
- if (link_state.interface != pl->link_config.interface) {
40+
- /* The interface has changed, force the link down and
41+
- * then reconfigure.
42+
- */
43+
- if (cur_link_state) {
44+
- phylink_link_down(pl);
45+
- cur_link_state = false;
46+
- }
47+
- phylink_major_config(pl, false, &link_state);
48+
- pl->link_config.interface = link_state.interface;
49+
+ if (mac_config && link_state.interface != pl->link_config.interface) {
50+
+ /* The interface has changed, so force the link down and then
51+
+ * reconfigure.
52+
+ */
53+
+ if (cur_link_state) {
54+
+ phylink_link_down(pl);
55+
+ cur_link_state = false;
56+
}
57+
+ phylink_major_config(pl, false, &link_state);
58+
+ pl->link_config.interface = link_state.interface;
59+
}
60+
61+
/* If configuration of the interface failed, force the link down

‎target/linux/generic/backport-6.18/785-v7.0-01-dt-bindings-phy-rename-transmit-amplitude.yaml-to-ph.patch‎

Lines changed: 235 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,235 @@
1+
From b7b4dcd96e3dfbb955d152c9ce4b490498b0f4b4 Mon Sep 17 00:00:00 2001
2+
From: Vladimir Oltean <vladimir.oltean@nxp.com>
3+
Date: Sun, 11 Jan 2026 11:39:30 +0200
4+
Subject: [PATCH 1/5] dt-bindings: phy: rename transmit-amplitude.yaml to
5+
phy-common-props.yaml
6+
7+
I would like to add more properties similar to tx-p2p-microvolt, and I
8+
don't think it makes sense to create one schema for each such property
9+
(transmit-amplitude.yaml, lane-polarity.yaml, transmit-equalization.yaml
10+
etc).
11+
12+
Instead, let's rename to phy-common-props.yaml, which makes it a more
13+
adequate host schema for all the above properties.
14+
15+
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
16+
Acked-by: Rob Herring (Arm) <robh@kernel.org>
17+
Link: https://patch.msgid.link/20260111093940.975359-2-vladimir.oltean@nxp.com
18+
Signed-off-by: Vinod Koul <vkoul@kernel.org>
19+
---
20+
.../{transmit-amplitude.yaml => phy-common-props.yaml} | 8 ++++----
21+
1 file changed, 4 insertions(+), 4 deletions(-)
22+
rename Documentation/devicetree/bindings/phy/{transmit-amplitude.yaml => phy-common-props.yaml} (90%)
23+
24+
--- a/Documentation/devicetree/bindings/phy/transmit-amplitude.yaml
25+
+++ /dev/null
26+
@@ -1,103 +0,0 @@
27+
-# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
28+
-%YAML 1.2
29+
----
30+
-$id: http://devicetree.org/schemas/phy/transmit-amplitude.yaml#
31+
-$schema: http://devicetree.org/meta-schemas/core.yaml#
32+
-
33+
-title: Common PHY and network PCS transmit amplitude property
34+
-
35+
-description:
36+
- Binding describing the peak-to-peak transmit amplitude for common PHYs
37+
- and network PCSes.
38+
-
39+
-maintainers:
40+
- - Marek Behún <kabel@kernel.org>
41+
-
42+
-properties:
43+
- tx-p2p-microvolt:
44+
- description:
45+
- Transmit amplitude voltages in microvolts, peak-to-peak. If this property
46+
- contains multiple values for various PHY modes, the
47+
- 'tx-p2p-microvolt-names' property must be provided and contain
48+
- corresponding mode names.
49+
-
50+
- tx-p2p-microvolt-names:
51+
- description: |
52+
- Names of the modes corresponding to voltages in the 'tx-p2p-microvolt'
53+
- property. Required only if multiple voltages are provided.
54+
-
55+
- If a value of 'default' is provided, the system should use it for any PHY
56+
- mode that is otherwise not defined here. If 'default' is not provided, the
57+
- system should use manufacturer default value.
58+
- minItems: 1
59+
- maxItems: 16
60+
- items:
61+
- enum:
62+
- - default
63+
-
64+
- # ethernet modes
65+
- - sgmii
66+
- - qsgmii
67+
- - xgmii
68+
- - 1000base-x
69+
- - 2500base-x
70+
- - 5gbase-r
71+
- - rxaui
72+
- - xaui
73+
- - 10gbase-kr
74+
- - usxgmii
75+
- - 10gbase-r
76+
- - 25gbase-r
77+
-
78+
- # PCIe modes
79+
- - pcie
80+
- - pcie1
81+
- - pcie2
82+
- - pcie3
83+
- - pcie4
84+
- - pcie5
85+
- - pcie6
86+
-
87+
- # USB modes
88+
- - usb
89+
- - usb-ls
90+
- - usb-fs
91+
- - usb-hs
92+
- - usb-ss
93+
- - usb-ss+
94+
- - usb-4
95+
-
96+
- # storage modes
97+
- - sata
98+
- - ufs-hs
99+
- - ufs-hs-a
100+
- - ufs-hs-b
101+
-
102+
- # display modes
103+
- - lvds
104+
- - dp
105+
- - dp-rbr
106+
- - dp-hbr
107+
- - dp-hbr2
108+
- - dp-hbr3
109+
- - dp-uhbr-10
110+
- - dp-uhbr-13.5
111+
- - dp-uhbr-20
112+
-
113+
- # camera modes
114+
- - mipi-dphy
115+
- - mipi-dphy-univ
116+
- - mipi-dphy-v2.5-univ
117+
-
118+
-dependencies:
119+
- tx-p2p-microvolt-names: [ tx-p2p-microvolt ]
120+
-
121+
-additionalProperties: true
122+
-
123+
-examples:
124+
- - |
125+
- phy: phy {
126+
- #phy-cells = <1>;
127+
- tx-p2p-microvolt = <915000>, <1100000>, <1200000>;
128+
- tx-p2p-microvolt-names = "2500base-x", "usb-hs", "usb-ss";
129+
- };
130+
--- /dev/null
131+
+++ b/Documentation/devicetree/bindings/phy/phy-common-props.yaml
132+
@@ -0,0 +1,103 @@
133+
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
134+
+%YAML 1.2
135+
+---
136+
+$id: http://devicetree.org/schemas/phy/phy-common-props.yaml#
137+
+$schema: http://devicetree.org/meta-schemas/core.yaml#
138+
+
139+
+title: Common PHY and network PCS properties
140+
+
141+
+description:
142+
+ Common PHY and network PCS properties, such as peak-to-peak transmit
143+
+ amplitude.
144+
+
145+
+maintainers:
146+
+ - Marek Behún <kabel@kernel.org>
147+
+
148+
+properties:
149+
+ tx-p2p-microvolt:
150+
+ description:
151+
+ Transmit amplitude voltages in microvolts, peak-to-peak. If this property
152+
+ contains multiple values for various PHY modes, the
153+
+ 'tx-p2p-microvolt-names' property must be provided and contain
154+
+ corresponding mode names.
155+
+
156+
+ tx-p2p-microvolt-names:
157+
+ description: |
158+
+ Names of the modes corresponding to voltages in the 'tx-p2p-microvolt'
159+
+ property. Required only if multiple voltages are provided.
160+
+
161+
+ If a value of 'default' is provided, the system should use it for any PHY
162+
+ mode that is otherwise not defined here. If 'default' is not provided, the
163+
+ system should use manufacturer default value.
164+
+ minItems: 1
165+
+ maxItems: 16
166+
+ items:
167+
+ enum:
168+
+ - default
169+
+
170+
+ # ethernet modes
171+
+ - sgmii
172+
+ - qsgmii
173+
+ - xgmii
174+
+ - 1000base-x
175+
+ - 2500base-x
176+
+ - 5gbase-r
177+
+ - rxaui
178+
+ - xaui
179+
+ - 10gbase-kr
180+
+ - usxgmii
181+
+ - 10gbase-r
182+
+ - 25gbase-r
183+
+
184+
+ # PCIe modes
185+
+ - pcie
186+
+ - pcie1
187+
+ - pcie2
188+
+ - pcie3
189+
+ - pcie4
190+
+ - pcie5
191+
+ - pcie6
192+
+
193+
+ # USB modes
194+
+ - usb
195+
+ - usb-ls
196+
+ - usb-fs
197+
+ - usb-hs
198+
+ - usb-ss
199+
+ - usb-ss+
200+
+ - usb-4
201+
+
202+
+ # storage modes
203+
+ - sata
204+
+ - ufs-hs
205+
+ - ufs-hs-a
206+
+ - ufs-hs-b
207+
+
208+
+ # display modes
209+
+ - lvds
210+
+ - dp
211+
+ - dp-rbr
212+
+ - dp-hbr
213+
+ - dp-hbr2
214+
+ - dp-hbr3
215+
+ - dp-uhbr-10
216+
+ - dp-uhbr-13.5
217+
+ - dp-uhbr-20
218+
+
219+
+ # camera modes
220+
+ - mipi-dphy
221+
+ - mipi-dphy-univ
222+
+ - mipi-dphy-v2.5-univ
223+
+
224+
+dependencies:
225+
+ tx-p2p-microvolt-names: [ tx-p2p-microvolt ]
226+
+
227+
+additionalProperties: true
228+
+
229+
+examples:
230+
+ - |
231+
+ phy: phy {
232+
+ #phy-cells = <1>;
233+
+ tx-p2p-microvolt = <915000>, <1100000>, <1200000>;
234+
+ tx-p2p-microvolt-names = "2500base-x", "usb-hs", "usb-ss";
235+
+ };

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