|
29 | 29 | #define RTMDIO_PHY_MAC_1G 3 |
30 | 30 | #define RTMDIO_PHY_MAC_2G_PLUS 1 |
31 | 31 |
|
32 | | -#define RTMDIO_PHY_POLL_MMD(dev, reg, bit) ((bit << 21) | (dev << 16) | reg) |
| 32 | +#define RTMDIO_PHY_POLL_MMD(dev, reg, bit) ((bit << 21) | (dev << 16) | (reg)) |
33 | 33 |
|
34 | 34 | /* MDIO bus registers/fields */ |
35 | 35 | #define RTMDIO_RUN BIT(0) |
|
42 | 42 | #define RTMDIO_838X_CMD_READ_C22 0 |
43 | 43 | #define RTMDIO_838X_CMD_READ_C45 BIT(1) |
44 | 44 | #define RTMDIO_838X_CMD_WRITE_C22 BIT(2) |
45 | | -#define RTMDIO_838X_CMD_WRITE_C45 BIT(1) | BIT(2) |
| 45 | +#define RTMDIO_838X_CMD_WRITE_C45 (BIT(1) | BIT(2)) |
46 | 46 | #define RTMDIO_838X_CMD_MASK GENMASK(2, 0) |
47 | 47 | #define RTMDIO_838X_SMI_ACCESS_PHY_CTRL_2 (0xa1c0) |
48 | 48 | #define RTMDIO_838X_SMI_ACCESS_PHY_CTRL_3 (0xa1c4) |
|
56 | 56 | #define RTMDIO_839X_CMD_READ_C22 0 |
57 | 57 | #define RTMDIO_839X_CMD_READ_C45 BIT(2) |
58 | 58 | #define RTMDIO_839X_CMD_WRITE_C22 BIT(3) |
59 | | -#define RTMDIO_839X_CMD_WRITE_C45 BIT(2) | BIT(3) |
| 59 | +#define RTMDIO_839X_CMD_WRITE_C45 (BIT(2) | BIT(3)) |
60 | 60 | #define RTMDIO_839X_CMD_MASK GENMASK(3, 0) |
61 | 61 | #define RTMDIO_839X_PHYREG_DATA_CTRL (0x03F0) |
62 | 62 | #define RTMDIO_839X_PHYREG_MMD_CTRL (0x03F4) |
|
70 | 70 | #define RTMDIO_930X_CMD_READ_C22 0 |
71 | 71 | #define RTMDIO_930X_CMD_READ_C45 BIT(1) |
72 | 72 | #define RTMDIO_930X_CMD_WRITE_C22 BIT(2) |
73 | | -#define RTMDIO_930X_CMD_WRITE_C45 BIT(1) | BIT(2) |
74 | | -#define RTMDIO_930X_CMD_MASK GENMASK(2, 0) | BIT(25) |
| 73 | +#define RTMDIO_930X_CMD_WRITE_C45 (BIT(1) | BIT(2)) |
| 74 | +#define RTMDIO_930X_CMD_MASK (GENMASK(2, 0) | BIT(25)) |
75 | 75 | #define RTMDIO_930X_SMI_ACCESS_PHY_CTRL_2 (0xCB78) |
76 | 76 | #define RTMDIO_930X_SMI_ACCESS_PHY_CTRL_3 (0xCB7C) |
77 | 77 | #define RTMDIO_930X_SMI_PORT0_15_POLLING_SEL (0xCA08) |
|
92 | 92 | #define RTMDIO_931X_CMD_READ_C22 0 |
93 | 93 | #define RTMDIO_931X_CMD_READ_C45 BIT(3) |
94 | 94 | #define RTMDIO_931X_CMD_WRITE_C22 BIT(4) |
95 | | -#define RTMDIO_931X_CMD_WRITE_C45 BIT(3) | BIT(4) |
| 95 | +#define RTMDIO_931X_CMD_WRITE_C45 (BIT(3) | BIT(4)) |
96 | 96 | #define RTMDIO_931X_CMD_MASK GENMASK(4, 0) |
97 | 97 | #define RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_1 (0x0C04) |
98 | 98 | #define RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_2 (0x0C08) |
|
0 commit comments