@@ -1465,19 +1465,16 @@ static int hdmi_phy_configure(struct dw_hdmi *hdmi)
14651465 const struct dw_hdmi_phy_data * phy = hdmi -> phy .data ;
14661466 const struct dw_hdmi_plat_data * pdata = hdmi -> plat_data ;
14671467 unsigned long mpixelclock = hdmi -> hdmi_data .video_mode .mpixelclock ;
1468- u8 tmds_cfg ;
14691468 int ret ;
14701469
14711470 dw_hdmi_phy_power_off (hdmi );
14721471
14731472 /* Control for TMDS Bit Period/TMDS Clock-Period Ratio */
1474- if (hdmi -> connector .scdc_present ) {
1475- drm_scdc_readb (hdmi -> ddc , SCDC_TMDS_CONFIG , & tmds_cfg );
1473+ if (hdmi -> connector .display_info .hdmi .scdc .supported ) {
14761474 if (mpixelclock > 340000000 )
1477- tmds_cfg |= 2 ;
1475+ drm_scdc_set_high_tmds_clock_ratio ( hdmi -> ddc , 1 ) ;
14781476 else
1479- tmds_cfg &= 0x1 ;
1480- drm_scdc_writeb (hdmi -> ddc , SCDC_TMDS_CONFIG , tmds_cfg );
1477+ drm_scdc_set_high_tmds_clock_ratio (hdmi -> ddc , 0 );
14811478 }
14821479
14831480 /* Leave low power consumption mode by asserting SVSRET. */
@@ -1593,7 +1590,7 @@ static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
15931590 bool is_hdmi2 = false;
15941591
15951592 if ((mode -> flags & DRM_MODE_FLAG_420_MASK ) ||
1596- hdmi -> connector .scdc_present )
1593+ hdmi -> connector .display_info . hdmi . scdc . supported )
15971594 is_hdmi2 = true;
15981595 /* Initialise info frame from DRM mode */
15991596 drm_hdmi_avi_infoframe_from_display_mode (& frame , mode , is_hdmi2 );
@@ -1757,6 +1754,7 @@ static void hdmi_av_composer(struct dw_hdmi *hdmi,
17571754 const struct drm_display_mode * mode )
17581755{
17591756 u8 inv_val , bytes ;
1757+ struct drm_hdmi_info * hdmi_info = & hdmi -> connector .display_info .hdmi ;
17601758 struct hdmi_vmode * vmode = & hdmi -> hdmi_data .video_mode ;
17611759 int hblank , vblank , h_de_hs , v_de_vs , hsync_len , vsync_len ;
17621760 unsigned int hdisplay , vdisplay ;
@@ -1774,7 +1772,7 @@ static void hdmi_av_composer(struct dw_hdmi *hdmi,
17741772 * when activate the scrambler feature.
17751773 */
17761774 inv_val = (vmode -> mpixelclock > 340000000 ||
1777- hdmi -> connector . lte_340mcsc_scramble ?
1775+ hdmi_info -> scdc . scrambling . low_rates ?
17781776 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
17791777 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE );
17801778
@@ -1843,22 +1841,22 @@ static void hdmi_av_composer(struct dw_hdmi *hdmi,
18431841 }
18441842
18451843 /* Scrambling Control */
1846- if (hdmi -> connector . scdc_present ) {
1844+ if (hdmi_info -> scdc . supported ) {
18471845 if (vmode -> mpixelclock > 340000000 ||
1848- hdmi -> connector . lte_340mcsc_scramble ) {
1846+ hdmi_info -> scdc . scrambling . low_rates ) {
18491847 drm_scdc_readb (& hdmi -> i2c -> adap , SCDC_SINK_VERSION ,
18501848 & bytes );
18511849 drm_scdc_writeb (& hdmi -> i2c -> adap , SCDC_SOURCE_VERSION ,
18521850 bytes );
1853- drm_scdc_writeb (& hdmi -> i2c -> adap , SCDC_TMDS_CONFIG , 1 );
1851+ drm_scdc_set_scrambling (& hdmi -> i2c -> adap , 1 );
18541852 hdmi_writeb (hdmi , (u8 )~HDMI_MC_SWRSTZ_TMDSSWRST_REQ ,
18551853 HDMI_MC_SWRSTZ );
18561854 hdmi_writeb (hdmi , 1 , HDMI_FC_SCRAMBLER_CTRL );
18571855 } else {
18581856 hdmi_writeb (hdmi , 0 , HDMI_FC_SCRAMBLER_CTRL );
18591857 hdmi_writeb (hdmi , (u8 )~HDMI_MC_SWRSTZ_TMDSSWRST_REQ ,
18601858 HDMI_MC_SWRSTZ );
1861- drm_scdc_writeb (& hdmi -> i2c -> adap , SCDC_TMDS_CONFIG , 0 );
1859+ drm_scdc_set_scrambling (& hdmi -> i2c -> adap , 0 );
18621860 }
18631861 }
18641862
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