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Tang Yun pingjayxurockchip
Tang Yun ping
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jayxurockchip
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arm: dts: rk3288: add dfi and dmc device nodes
Add dfi and dmc nodes in the device tree for the ARM rk3288 SoC. To support ddr frequency scaling function, we need enable dmc and dfi nodes. Change-Id: Ib796c08c694e74e0da3319d2797e95aecf3e7e73 Signed-off-by: Tang Yun ping <typ@rock-chips.com>
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‎arch/arm/boot/dts/rk3288-android.dtsi‎

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*/
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#include <dt-bindings/pwm/pwm.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/soc/rockchip-system-status.h>
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#include "rk3288-dram-default-timing.dtsi"
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/ {
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chosen {
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bootargs = "earlycon=uart8250,mmio32,0xff690000";
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};
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/delete-node/ dmc@ff610000;
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dfi: dfi {
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compatible = "rockchip,rk3288-dfi";
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rockchip,pmu = <&pmu>;
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rockchip,grf = <&grf>;
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status = "disabled";
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};
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dmc: dmc {
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compatible = "rockchip,rk3288-dmc";
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devfreq-events = <&dfi>;
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clocks = <&cru SCLK_DDRCLK>, <&cru PCLK_PUBL0>,
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<&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL1>,
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<&cru PCLK_DDRUPCTL1>;
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clock-names = "dmc_clk", "pclk_phy0", "pclk_upctl0",
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"pclk_phy1", "pclk_upctl1";
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upthreshold = <55>;
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downdifferential = <10>;
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operating-points-v2 = <&dmc_opp_table>;
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vop-dclk-mode = <0>;
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min-cpu-freq = <600000>;
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rockchip,ddr_timing = <&ddr_timing>;
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system-status-freq = <
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/*system status freq(KHz)*/
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SYS_STATUS_NORMAL 396000
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SYS_STATUS_REBOOT 396000
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SYS_STATUS_SUSPEND 192000
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SYS_STATUS_VIDEO_1080P 300000
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SYS_STATUS_VIDEO_4K 396000
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SYS_STATUS_PERFORMANCE 528000
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SYS_STATUS_BOOST 396000
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SYS_STATUS_DUALVIEW 396000
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SYS_STATUS_ISP 396000
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>;
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auto-min-freq = <192000>;
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auto-freq-en = <0>;
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status = "diasbled";
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};
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dmc_opp_table: opp_table2 {
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compatible = "operating-points-v2";
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opp-192000000 {
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opp-hz = /bits/ 64 <192000000>;
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opp-microvolt = <1100000>;
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};
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opp-300000000 {
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opp-hz = /bits/ 64 <300000000>;
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opp-microvolt = <1100000>;
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};
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opp-396000000 {
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opp-hz = /bits/ 64 <396000000>;
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opp-microvolt = <1100000>;
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};
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opp-528000000 {
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opp-hz = /bits/ 64 <528000000>;
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opp-microvolt = <1150000>;
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};
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};
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reserved-memory {
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ramoops_mem: ramoops@00000000 {
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reg = <0x0 0x8000000 0x0 0xF0000>;

‎arch/arm/boot/dts/rk3288-dram-default-timing.dtsi‎

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/*
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* Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <dt-bindings/clock/rockchip-ddr.h>
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#include <dt-bindings/memory/rk3288-dram.h>
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/ {
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ddr_timing: ddr_timing {
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compatible = "rockchip,ddr-timing";
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ddr3_speed_bin = <DDR3_DEFAULT>;
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pd_idle = <0x40>;
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sr_idle = <0x1>;
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auto_pd_dis_freq = <800>;
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auto_sr_dis_freq = <800>;
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ddr3_dll_dis_freq = <300>;
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phy_dll_dis_freq = <250>;
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ddr3_odt_dis_freq = <333>;
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phy_ddr3_odt_dis_freq = <333>;
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ddr3_drv = <DDR3_DS_40ohm>;
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ddr3_odt = <DDR3_ODT_120ohm>;
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phy_ddr3_drv = <PHY_DDR3_RON_34ohm>;
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phy_ddr3_odt = <PHY_DDR3_RTT_155ohm>;
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lpddr2_drv = <LP2_DS_40ohm>;
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phy_lpddr2_drv = <PHY_LP23_RON_35ohm>;
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lpddr3_odt_dis_freq = <333>;
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phy_lpddr3_odt_dis_freq = <333>;
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lpddr3_drv = <LP3_DS_40ohm>;
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lpddr3_odt = <LP3_ODT_240ohm>;
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phy_lpddr3_drv = <PHY_LP23_RON_35ohm>;
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phy_lpddr3_odt = <PHY_LP23_RTT_155ohm>;
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};
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};

‎include/dt-bindings/memory/rk3288-dram.h‎

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/*
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* Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef _DT_BINDINGS_DRAM_ROCKCHIP_RK3288_H
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#define _DT_BINDINGS_DRAM_ROCKCHIP_RK3288_H
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#define DDR3_DS_34ohm (34)
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#define DDR3_DS_40ohm (40)
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#define DDR3_ODT_DIS (0)
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#define DDR3_ODT_40ohm (40)
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#define DDR3_ODT_60ohm (60)
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#define DDR3_ODT_120ohm (120)
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#define LP2_DS_34ohm (34)
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#define LP2_DS_40ohm (40)
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#define LP2_DS_48ohm (48)
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#define LP2_DS_60ohm (60)
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#define LP2_DS_68_6ohm (68) /* optional */
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#define LP2_DS_80ohm (80)
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#define LP2_DS_120ohm (120) /* optional */
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#define LP3_DS_34ohm (34)
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#define LP3_DS_40ohm (40)
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#define LP3_DS_48ohm (48)
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#define LP3_DS_60ohm (60)
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#define LP3_DS_80ohm (80)
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#define LP3_DS_34D_40U (3440)
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#define LP3_DS_40D_48U (4048)
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#define LP3_DS_34D_48U (3448)
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#define LP3_ODT_DIS (0)
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#define LP3_ODT_60ohm (60)
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#define LP3_ODT_120ohm (120)
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#define LP3_ODT_240ohm (240)
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/* PHY DRV ODT strength*/
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#define PHY_DDR3_RON_114ohm (7)
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#define PHY_DDR3_RON_95ohm (4)
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#define PHY_DDR3_RON_81ohm (5)
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#define PHY_DDR3_RON_71ohm (0xc)
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#define PHY_DDR3_RON_63ohm (0xd)
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#define PHY_DDR3_RON_57ohm (0xe)
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#define PHY_DDR3_RON_52ohm (0xf)
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#define PHY_DDR3_RON_47ohm (0xa)
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#define PHY_DDR3_RON_44ohm (0xb)
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#define PHY_DDR3_RON_41ohm (0x8)
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#define PHY_DDR3_RON_38ohm (0x9)
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#define PHY_DDR3_RON_34ohm (0x19)
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#define PHY_DDR3_RON_30ohm (0x1b)
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#define PHY_DDR3_RON_26ohm (0x1c)
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#define PHY_DDR3_RON_23ohm (0x15)
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#define PHY_DDR3_RON_20ohm (0x12)
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#define PHY_DDR3_RON_18ohm (0x11)
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#define PHY_DDR3_RTT_368ohm (0x1)
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#define PHY_DDR3_RTT_155ohm (0x2)
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#define PHY_DDR3_RTT_113ohm (0x3)
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#define PHY_DDR3_RTT_80ohm (0x6)
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#define PHY_DDR3_RTT_64ohm (0x7)
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#define PHY_DDR3_RTT_54ohm (0x4)
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#define PHY_DDR3_RTT_40ohm (0xc)
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#define PHY_DDR3_RTT_30ohm (0xf)
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#define PHY_LP23_RON_110ohm (4)
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#define PHY_LP23_RON_83ohm (0xc)
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#define PHY_LP23_RON_73ohm (0xd)
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#define PHY_LP23_RON_66ohm (0xe)
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#define PHY_LP23_RON_60ohm (0xf)
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#define PHY_LP23_RON_55ohm (0xa)
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#define PHY_LP23_RON_51ohm (0xb)
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#define PHY_LP23_RON_44ohm (0x9)
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#define PHY_LP23_RON_39ohm (0x19)
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#define PHY_LP23_RON_35ohm (0x1b)
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#define PHY_LP23_RON_30ohm (0x1c)
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#define PHY_LP23_RON_26ohm (0x16)
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#define PHY_LP23_RON_22ohm (0x10)
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#define PHY_LP23_RTT_368ohm (0x1)
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#define PHY_LP23_RTT_155ohm (0x2)
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#define PHY_LP23_RTT_113ohm (0x3)
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#define PHY_LP23_RTT_80ohm (0x6)
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#define PHY_LP23_RTT_64ohm (0x7)
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#define PHY_LP23_RTT_54ohm (0x4)
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#define PHY_LP23_RTT_40ohm (0xc)
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#define PHY_LP23_RTT_30ohm (0xf)
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#endif /*_DT_BINDINGS_DRAM_ROCKCHIP_RK3288_H*/

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