@@ -62,17 +62,57 @@ General Methods
6262
6363 Write out the bytes from the buffer. Returns the number of bytes written.
6464
65- .. method :: I2CTarget.irq(handler=None, trigger=0, hard=False )
65+ .. method :: I2CTarget.memaddr( )
6666
67- Configure an IRQ handler.
67+ Get the last memory address that was selected by the controller. Returns an
68+ integer.
69+
70+ .. method :: I2CTarget.irq(handler=None, trigger=IRQ_END_READ|IRQ_END_WRITE, hard=False)
71+
72+ Configure an IRQ *handler * to be called when an event occurs. The possible events are
73+ given by the following constants, which can be or'd together and passed to the *trigger *
74+ argument:
75+
76+ - ``IRQ_ADDR_MATCH_READ `` indicates that the target was addressed by a
77+ controller for a read transaction.
78+ - ``IRQ_ADDR_MATCH_READ `` indicates that the target was addressed by a
79+ controller for a write transaction.
80+ - ``IRQ_READ_REQ `` indicates that the controller is requesting data, and this
81+ request must be satisfied by calling `I2CTarget.write ` with the data to be
82+ passed back to the controller.
83+ - ``IRQ_WRITE_REQ `` indicates that the controller has written data, and the
84+ data must be read by calling `I2CTarget.readinto `.
85+ - ``IRQ_END_READ `` indicates that the controller has finished a read transaction.
86+ - ``IRQ_END_WRITE `` indicates that the controller has finished a write transaction.
87+
88+ Not all triggers are available on all ports. If a port has the constant then that
89+ event is available.
90+
91+ Note the following restrictions:
92+
93+ - ``IRQ_ADDR_MATCH_READ ``, ``IRQ_ADDR_MATCH_READ ``, ``IRQ_READ_REQ `` and
94+ ``IRQ_WRITE_REQ `` must be handled by a hard IRQ callback (with the *hard * argument
95+ set to ``True ``). This is because these events have very strict timing requirements
96+ and must usually be satisfied synchronously with the hardware event.
97+
98+ - ``IRQ_END_READ `` and ``IRQ_END_WRITE `` may be handled by either a soft or hard
99+ IRQ callback (although note that all events must be registered with the same handler,
100+ so if any events need a hard callback then all events must be hard).
101+
102+ - If a memory buffer has been supplied in the constructor then ``IRQ_END_WRITE ``
103+ is not emitted for the transaction that writes the memory address. This is to
104+ allow ``IRQ_END_READ `` and ``IRQ_END_WRITE `` to function correctly as soft IRQ
105+ callbacks, where the IRQ handler may be called quite some time after the actual
106+ hardware event.
68107
69108Constants
70109---------
71110
72- .. data :: I2CTarget.IRQ_ADDR_MATCH
111+ .. data :: I2CTarget.IRQ_ADDR_MATCH_READ
112+ .. data :: I2CTarget.IRQ_ADDR_MATCH_WRITE
73113 I2CTarget.IRQ_READ_REQ
74114 I2CTarget.IRQ_WRITE_REQ
75- I2CTarget.IRQ_END
76- I2CTarget.IRQ_STOP
115+ I2CTarget.IRQ_END_READ
116+ I2CTarget.IRQ_END_WRITE
77117
78118 IRQ trigger sources.
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