Peer review fixes

Author: dgarske

hal/tpm_io_mmio.c

@@ -37,8 +37,8 @@
 #ifdef WOLFTPM_INCLUDE_IO_FILE
 #ifdef WOLFTPM_MMIO
 
-#ifndef MIMO_BASE_ADDRESS
-#define MIMO_BASE_ADDRESS 0xFE000000u
+#ifndef MMIO_BASE_ADDRESS
+#define MMIO_BASE_ADDRESS 0xFE000000u
 #endif
 
 #ifndef WOLFTPM_ADV_IO
@@ -108,14 +108,14 @@ int TPM2_IoCb_Mmio(TPM2_CTX *ctx, int isRead, word32 addr, byte* buf, word16 siz
         return TPM_RC_FAILURE;
     }
 
-    effectiveAddr = MIMO_BASE_ADDRESS + addr;
+    effectiveAddr = MMIO_BASE_ADDRESS + addr;
 
     /* FIFO registers use the same address for every access
      * (hardware auto-increments internally).
-     * Non-FIFO registers need the address advanced for multi-byte access.
-     * TPM_DATA_FIFO offset=0x0024, TPM_XDATA_FIFO offset=0x0083 */
+     * Non-FIFO registers need the address advanced for multi-byte access. */
     regOffset = addr & 0x0FFFu;
-    isFifo = (regOffset == 0x0024u || regOffset == 0x0083u);
+    isFifo = (regOffset == TPM_TIS_DATA_FIFO_OFFSET ||
+              regOffset == TPM_TIS_XDATA_FIFO_OFFSET);
 
     /* IO for 32-bit aligned */
     for (i = 0; ((size_t)size - i) >= sizeof(word32); i += sizeof(word32)) {

src/tpm2_tis.c

@@ -84,8 +84,8 @@ enum tpm_tis_status {
 #define TPM_INT_STATUS(l)       (TPM_BASE_ADDRESS | 0x0010u | ((l) << 12u))
 #define TPM_STS(l)              (TPM_BASE_ADDRESS | 0x0018u | ((l) << 12u))
 #define TPM_BURST_COUNT(l)      (TPM_BASE_ADDRESS | 0x0019u | ((l) << 12u))
-#define TPM_DATA_FIFO(l)        (TPM_BASE_ADDRESS | 0x0024u | ((l) << 12u))
-#define TPM_XDATA_FIFO(l)       (TPM_BASE_ADDRESS | 0x0083u | ((l) << 12u))
+#define TPM_DATA_FIFO(l)        (TPM_BASE_ADDRESS | TPM_TIS_DATA_FIFO_OFFSET | ((l) << 12u))
+#define TPM_XDATA_FIFO(l)       (TPM_BASE_ADDRESS | TPM_TIS_XDATA_FIFO_OFFSET | ((l) << 12u))
 
 
 /* this option enables named semaphore protection on TIS commands for protected

src/tpm2_wrap.c

@@ -4471,7 +4471,7 @@ int wolfTPM2_VerifyHash(WOLFTPM2_DEV* dev, WOLFTPM2_KEY* key,
         }
         else if (pub->type == TPM_ALG_RSA) {
             hashAlg = pub->parameters.rsaDetail.scheme.details.anySig.hashAlg;
-            if (hashAlg == TPM_ALG_NULL || hashAlg == 0)
+            if (hashAlg == TPM_ALG_NULL || hashAlg == TPM_ALG_ERROR)
                 hashAlg = TPM_ALG_SHA256;
         }
     }
@@ -4688,6 +4688,7 @@ int wolfTPM2_ECDHEGenZ(WOLFTPM2_DEV* dev, WOLFTPM2_KEY* parentKey,
         printf("TPM2_ZGen_2Phase failed %d: %s\n", rc,
             wolfTPM2_GetRCString(rc));
     #endif
+        TPM2_ForceZero(&outZGen2Ph, sizeof(outZGen2Ph));
         return rc;
     }
 

wolftpm/tpm2_tis.h

@@ -41,6 +41,10 @@
 
 #define TPM_TIS_READY_MASK 0x01
 
+/* TIS register offsets (without base address or locality) */
+#define TPM_TIS_DATA_FIFO_OFFSET   0x0024u
+#define TPM_TIS_XDATA_FIFO_OFFSET  0x0083u
+
 /* Typically only 0-2 wait states are required */
 #ifndef TPM_TIS_MAX_WAIT
 #define TPM_TIS_MAX_WAIT   3