Fix Fenrir F-1227: MMIO register access for multi-byte read/write

Author: dgarske

hal/tpm_io_mmio.c

@@ -100,6 +100,8 @@ int TPM2_IoCb_Mmio(TPM2_CTX *ctx, int isRead, word32 addr, byte* buf, word16 siz
 {
     size_t i;
     word32 effectiveAddr;
+    word32 regOffset;
+    int isFifo;
 
     /* Bounds check to prevent address wrap-around */
     if (addr >= TPM_MMIO_MAX_OFFSET) {
@@ -108,12 +110,21 @@ int TPM2_IoCb_Mmio(TPM2_CTX *ctx, int isRead, word32 addr, byte* buf, word16 siz
 
     effectiveAddr = MIMO_BASE_ADDRESS + addr;
 
+    /* FIFO registers use the same address for every access
+     * (hardware auto-increments internally).
+     * Non-FIFO registers need the address advanced for multi-byte access.
+     * TPM_DATA_FIFO offset=0x0024, TPM_XDATA_FIFO offset=0x0083 */
+    regOffset = addr & 0x0FFFu;
+    isFifo = (regOffset == 0x0024u || regOffset == 0x0083u);
+
     /* IO for 32-bit aligned */
     for (i = 0; ((size_t)size - i) >= sizeof(word32); i += sizeof(word32)) {
         if (isRead)
             TPM2_Mmio_Read32(effectiveAddr, buf + i);
         else
             TPM2_Mmio_Write32(effectiveAddr, buf + i);
+        if (!isFifo)
+            effectiveAddr += sizeof(word32);
     }
 
     /* IO for unaligned remainder */
@@ -122,6 +133,8 @@ int TPM2_IoCb_Mmio(TPM2_CTX *ctx, int isRead, word32 addr, byte* buf, word16 siz
             TPM2_Mmio_Read8(effectiveAddr, buf + i);
         else
             TPM2_Mmio_Write8(effectiveAddr, buf + i);
+        if (!isFifo)
+            effectiveAddr++;
     }
 
     (void)ctx;