Skip to content

Commit f3a9d4a

Browse files
author
gojimmypi
committed
Espressif Benchmark ESP-IDF 4.4 fixes
1 parent 4bd78e5 commit f3a9d4a

3 files changed

Lines changed: 28 additions & 10 deletions

File tree

IDE/Espressif/ESP-IDF/examples/wolfssl_benchmark/VisualGDB/wolfssl_benchmark_IDF_v4.4_ESP32.vgdbproj

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
<?xml version="1.0"?>
2-
<VisualGDBProjectSettings2 xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xsd="http://www.w3.org/2001/XMLSchema">
2+
<VisualGDBProjectSettings2 xmlns:xsd="http://www.w3.org/2001/XMLSchema" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
33
<Project xsi:type="com.visualgdb.project.external.esp-idf">
44
<CustomSourceDirectories>
55
<Directories />
@@ -220,7 +220,7 @@
220220
<DebugMethod>
221221
<ID>openocd</ID>
222222
<Configuration xsi:type="com.visualgdb.edp.openocd.settings.esp32">
223-
<CommandLine>-f interface/tigard.cfg -c "adapter_khz 15000" -f target/esp32.cfg</CommandLine>
223+
<CommandLine>-f interface/ftdi/tigard.cfg -c "adapter_khz 15000" -f target/esp32.cfg</CommandLine>
224224
<ExtraParameters>
225225
<Frequency xsi:nil="true" />
226226
<BoostedFrequency xsi:nil="true" />

wolfcrypt/benchmark/benchmark.c

Lines changed: 18 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1274,11 +1274,19 @@ static const char* bench_result_words3[][5] = {
12741274
#endif /* WOLFSSL_BENCHMARK_TIMER_DEBUG */
12751275

12761276
/* The ESP32 (both Xtensa and RISC-V have raw CPU counters). */
1277-
#define HAVE_GET_CYCLES
1278-
#define INIT_CYCLE_COUNTER do { \
1279-
ESP_LOGV(TAG, "INIT_CYCLE_COUNTER"); \
1280-
esp_cpu_set_cycle_count(0); \
1281-
} while (0);
1277+
#if ESP_IDF_VERSION_MAJOR >= 5
1278+
/* esp_cpu_set_cycle_count() introduced in ESP-IDF v5 */
1279+
#define HAVE_GET_CYCLES
1280+
#define INIT_CYCLE_COUNTER do { \
1281+
ESP_LOGV(TAG, "INIT_CYCLE_COUNTER"); \
1282+
esp_cpu_set_cycle_count(0); \
1283+
} while (0);
1284+
#else
1285+
#define HAVE_GET_CYCLES
1286+
#define INIT_CYCLE_COUNTER do { \
1287+
ESP_LOGV(TAG, "INIT_CYCLE_COUNTER"); \
1288+
} while (0);
1289+
#endif
12821290

12831291
#define BEGIN_ESP_CYCLES do { \
12841292
ESP_LOGV(TAG, "BEGIN_ESP_CYCLES"); \
@@ -1494,7 +1502,11 @@ static const char* bench_result_words3[][5] = {
14941502
* when resetting CPU cycle counter? FreeRTOS tick collison?
14951503
* thisVal = esp_cpu_get_cycle_count(); See also, above
14961504
* or thisVal = xthal_get_ccount(); */
1497-
_esp_cpu_count_last = esp_cpu_get_cycle_count();
1505+
#if ESP_IDF_VERSION_MAJOR < 5
1506+
_esp_cpu_count_last = xthal_get_ccount();
1507+
#else
1508+
_esp_cpu_count_last = esp_cpu_get_cycle_count();
1509+
#endif
14981510
#endif
14991511

15001512
/* Return the 64 bit extended total from 32 bit counter. */

wolfcrypt/src/port/Espressif/esp32_util.c

Lines changed: 8 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -34,8 +34,9 @@
3434
/* Espressif */
3535
#include <esp_log.h>
3636
#include <esp_err.h>
37-
#include <hal/efuse_hal.h>
38-
37+
#if ESP_IDF_VERSION_MAJOR > 4
38+
#include <hal/efuse_hal.h>
39+
#endif
3940
/* wolfSSL */
4041
#include <wolfssl/wolfcrypt/wolfmath.h> /* needed to print MATH_INT_T value */
4142
#include <wolfssl/wolfcrypt/types.h>
@@ -452,7 +453,10 @@ int esp_ShowHardwareAcclerationSettings(void)
452453
*/
453454
int ShowExtendedSystemInfo(void)
454455
{
456+
#if ESP_IDF_VERSION_MAJOR > 4
455457
unsigned chip_rev = -1;
458+
#endif
459+
456460
#ifdef HAVE_ESP_CLK
457461
/* esp_clk.h is private */
458462
int cpu_freq = 0;
@@ -470,8 +474,10 @@ int ShowExtendedSystemInfo(void)
470474
"Some extended system details not available.");
471475
#endif /* else not HAVE_WC_INTROSPECTION */
472476

477+
#if ESP_IDF_VERSION_MAJOR > 4
473478
chip_rev = efuse_hal_chip_revision();
474479
ESP_LOGI(TAG, "Chip revision: v%d.%d", chip_rev / 100, chip_rev % 100);
480+
#endif
475481

476482
#ifdef HAVE_ESP_CLK
477483
cpu_freq = esp_clk_cpu_freq();

0 commit comments

Comments
 (0)