Docs/updates: Improve technical accuracy and clarity of Verilog documentation

[SouparnaChatterjee]

Fixes #531

Changes done:

• Corrected technical inaccuracies regarding FPGA usage and synthesis
• Clarified structural vs behavioral Verilog generation
• Corrected ALU classification
• Improved grammar and documentation tone
• Standardized formatting and headings

Screenshots:
N/A (Documentation-only changes)

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• Tried squashing the commits into one

Summary by CodeRabbit

• Documentation

  • Replaced the Introduction page with a new, reorganized version featuring clear sections, images, and a video overview
  • Restructured and expanded Circuit-to-Verilog guidance with step-by-step instructions, clearer headings, and improved examples

• Style

  • Added improved figure and caption styling for better readability and visual polish

[coderabbitai]

No actionable comments were generated in the recent review. 🎉

ℹ️ Recent review info

Configuration used: Organization UI

Review profile: CHILL

Plan: Pro

📥 Commits

Reviewing files that changed from the base of the PR and between db832b9 and a2f1095.

📒 Files selected for processing (1)

• docs/chapter1/1introduction.md

💤 Files with no reviewable changes (1)

• docs/chapter1/1introduction.md

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Walkthrough

Deletes docs/chapter1/1introduction.md and adds a new docs/chapter1/1introduction.mdx with frontmatter and restructured introduction content. Substantially rewrites docs/chapter8/1circuittoverilog.md, reorganizing headings, converting procedural steps to numbered sections, adding figure/media markup, and clarifying Verilog-related wording. Adds figure/figcaption styling to src/css/custom.css. Updates package.json Node engine requirement from ">=18.0" to ">=18". No exported or public APIs were changed.

Possibly related PRs

• CircuitVerse/CircuitVerseDocs PR 405: migration from docsify to Docusaurus and related MDX/CSS media-handling adjustments.

🚥 Pre-merge checks | ✅ 4 | ❌ 1

❌ Failed checks (1 warning)

Check name	Status	Explanation	Resolution
Out of Scope Changes check	⚠️ Warning	Changes to package.json (Node version requirement) and intro file migration (.md to .mdx) are out of scope from issue #531 which focuses solely on Verilog documentation accuracy and clarity.	Remove the package.json version change and consider the introduction file migration as a separate documentation improvement PR aligned with specific requirements.

✅ Passed checks (4 passed)

Check name	Status	Explanation
Description Check	✅ Passed	Check skipped - CodeRabbit’s high-level summary is enabled.
Title check	✅ Passed	The title accurately reflects the main objective of improving Verilog documentation technical accuracy and clarity, which aligns with the primary changes in docs/chapter8/1circuittoverilog.md.
Linked Issues check	✅ Passed	The PR addresses all coding requirements from issue #531: clarifying FPGA synthesis needs, correcting ALU classification, specifying structural Verilog generation, and improving grammar/documentation tone throughout the Verilog documentation.
Docstring Coverage	✅ Passed	No functions found in the changed files to evaluate docstring coverage. Skipping docstring coverage check.

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Actionable comments posted: 1

🧹 Nitpick comments (2)

docs/chapter1/1introduction.mdx (1)

14-17: Use semantic <figure> + <figcaption> for consistency with the rest of this PR.

These captioned images are currently split into markdown image + italic text. Converting to semantic figure markup will align with src/css/custom.css and improve consistency.

Also applies to: 30-33, 40-43

docs/chapter8/1circuittoverilog.md (1)

32-35: Consider using <figure>/<figcaption> instead of centered <div><em>... captions.

This would standardize media semantics across docs and reuse the new figure styles more consistently.

Also applies to: 44-47

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ℹ️ Review info

Configuration used: Organization UI

Review profile: CHILL

Plan: Pro

📥 Commits

Reviewing files that changed from the base of the PR and between f6deeb5 and e3419dd.

📒 Files selected for processing (4)

• docs/chapter1/1introduction.md
• docs/chapter1/1introduction.mdx
• docs/chapter8/1circuittoverilog.md
• src/css/custom.css