3737#ifdef WOLFTPM_INCLUDE_IO_FILE
3838#ifdef WOLFTPM_MMIO
3939
40- #ifndef MIMO_BASE_ADDRESS
41- #define MIMO_BASE_ADDRESS 0xFE000000u
40+ #ifndef MMIO_BASE_ADDRESS
41+ #define MMIO_BASE_ADDRESS 0xFE000000u
4242#endif
4343
4444#ifndef WOLFTPM_ADV_IO
@@ -100,20 +100,31 @@ int TPM2_IoCb_Mmio(TPM2_CTX *ctx, int isRead, word32 addr, byte* buf, word16 siz
100100{
101101 size_t i ;
102102 word32 effectiveAddr ;
103+ word32 regOffset ;
104+ int isFifo ;
103105
104106 /* Bounds check to prevent address wrap-around */
105107 if (addr >= TPM_MMIO_MAX_OFFSET ) {
106108 return TPM_RC_FAILURE ;
107109 }
108110
109- effectiveAddr = MIMO_BASE_ADDRESS + addr ;
111+ effectiveAddr = MMIO_BASE_ADDRESS + addr ;
112+
113+ /* FIFO registers use the same address for every access
114+ * (hardware auto-increments internally).
115+ * Non-FIFO registers need the address advanced for multi-byte access. */
116+ regOffset = addr & 0x0FFFu ;
117+ isFifo = (regOffset == TPM_TIS_DATA_FIFO_OFFSET ||
118+ regOffset == TPM_TIS_XDATA_FIFO_OFFSET );
110119
111120 /* IO for 32-bit aligned */
112121 for (i = 0 ; ((size_t )size - i ) >= sizeof (word32 ); i += sizeof (word32 )) {
113122 if (isRead )
114123 TPM2_Mmio_Read32 (effectiveAddr , buf + i );
115124 else
116125 TPM2_Mmio_Write32 (effectiveAddr , buf + i );
126+ if (!isFifo )
127+ effectiveAddr += sizeof (word32 );
117128 }
118129
119130 /* IO for unaligned remainder */
@@ -122,6 +133,8 @@ int TPM2_IoCb_Mmio(TPM2_CTX *ctx, int isRead, word32 addr, byte* buf, word16 siz
122133 TPM2_Mmio_Read8 (effectiveAddr , buf + i );
123134 else
124135 TPM2_Mmio_Write8 (effectiveAddr , buf + i );
136+ if (!isFifo )
137+ effectiveAddr ++ ;
125138 }
126139
127140 (void )ctx ;
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